16-mb (1024k x 16) static ram cy62167dv20 mobl2? cypresssemiconductorcorporation ? 3901northfirststreet ? sanjose , ca 95134 ? 408-943-2600 document #: 38-05327 rev. *b revised january 2, 2004 features ? very high speed: 55 ns and 70 ns ? wide voltage range: 1.65v to 2.2v ? ultra-low active power ? typical active current: 1.5 ma @ f = 1 mhz ? typical active current: 18 ma @ f = f max ? ultra-low standby power ? easy memory expansion with ce 1 , ce 2 , and oe features ? automatic power-down when deselected ? cmos for optimum speed/power ? packages offered in a 48-ball fbga functional description [1] the cy62167dv20 is a high-performance cmos static ram organized as 1024k words by 16 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life tm (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. the device can be put into standby mode reducing power consumption by more than 99% when deselected chip enable 1 ( ce 1 ) high or chip enable 2 (ce 2 ) low or both bhe and ble are high . the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected chip enable 1 ( ce 1 ) high or chip enable 2 (ce 2 ) low , outputs are disabled ( oe high), both byte high enable and byte low enable are disabled ( bhe , ble high) or during a write operation (chip enable 1 ( ce 1 ) low and chip enable 2 (ce 2 ) high and we low). writing to the device is accomplished by taking chip enable 1 ( ce 1 ) low and chip enable 2 (ce 2 ) high and write enable (we) input low. if byte low enable ( ble ) is low, then da s pins (a 0 through a 19 ). if byte high enable ( bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the ad reading from the device is accomplished by taking chip enable 1 ( ce 1 ) low and chip enable 2 (ce 2 ) high and output enable (oe) low while forcing the write enable (we) high. if byte low enable (<> o 7 . if byte high enable ( bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of re ad and write modes. note: 1. for best practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypress .com. 1024k x 16 ram array i / o 0 ? i / o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i / o 8 ? i / o 1 5 w e ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 1 0 power-down circuit bhe ble ce 2 ce 1 ce 2 ce 1 a 19 2048 x 512 x 16 logic block diagram
cy62167dv20 mobl2? document #: 38-05327 rev. *b page 2 of 10 notes: 2. dnu pins are to be connected to v ss or left open. 3. nc pins are not connected on the die. pin configuration [2, 3.] we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 dnu vcc
cy62167dv20 mobl2? document #: 38-05327 rev. *b page 3 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65c to +150c ambient temperature with power applied ............................................. ?55c to +125c supply voltage to ground potential ......................................... - 0.2 v to v ccmax + 0.2v dc voltage applied to outputs in high-z state [4, 5.] ......................... - 0.2 v to v ccmax + 0.2v dc input voltage [4, 5.] ...................... - 0.2 v to v ccmax + 0.2v output current into outputs (low) ............................. 20 ma static discharge voltage ......................................... > 2001v (per mil-std-883, method 3015) latch-up current ..................................................... > 200 ma operating range range ambient temperature (t a ) v cc [6] industrial - 40 o c to +85 o c 1.65v to 2.2v product portfolio product v cc range(v) speed (ns) power dissipation operating, icc (ma) standby, i sb2 ( m a) f = 1 mhz f = f max min. typ. max. typ. [7] max. typ. [7] max. typ. [7] max. CY62167DV20L 1.65 1.8 2.2 55 1.5 5 18 35 2.5 40 70 15 30 2.5 40 CY62167DV20Ll 1.65 1.8 2.2 55 1.5 5 18 35 2.5 30 70 15 30 2.5 30 dc electrical characteristics (over the operating range) parameter description test conditions cy62167dv20-55 cy62167dv20-70 unit min. typ. [7] max. min. typ. [7] max. v oh output high voltage i oh = - 0.1 ma v cc = 1.65v 1.4 1.4 v v ol output low voltage i ol = 0.1 ma v cc = 1.65v 0.2 0.2 v v ih input high voltage 1.4 v cc + 0.2 1.4 v cc + 0.2 v v il input low voltage ?0.2 0.4 ?0.2 0.4 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 m a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?1 +1 m a i cc v cc operating supply current f = f max = 1/t rc vcc = 2.2v, i out = 0ma, cmos level 18 35 15 30 ma f = 1 mhz 1.5 5 1.5 5 i sb1 automatic ce power-down current - cmos inputs ce 1 > v cc - 0.2v, ce 2 < 0.2v, v in > v cc - 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 ( oe , we , bhe and ble ) l 2.5 40 2.5 40 m a ll 2.5 30 2.5 30 i sb2 automatic ce power-down current - cmos inputs ce 1 > v cc - 0.2v, ce 2 < 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0, v cc =2.2v l 2.5 40 2.5 40 m a ll 2.5 30 2.5 30 capacitance [8] parameter description test conditions max. unit c in input capacitance ta = 25c, f = 1 mhz v cc = v cc(typ) 8 pf c out output capacitance 10 pf 4. v il(min.) = - 2.0v for pulse durations less than 20 ns. 5. v ih(max) = v cc + 0.75v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 m s ramp time from 0 to v cc (min) and 100 m s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ.) , t a = 25c. 8. tested initially and after any design or process changes that may affect these parameters.
cy62167dv20 mobl2? document #: 38-05327 rev. *b page 4 of 10 ac test loads and waveforms data retention waveform [10] thermal resistance parameter description test conditions bga unit q ja thermal resistance (junction to ambient) [8] still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 55 c/w q jc thermal resistance (junction to case) [8] 16 c/w v cc typ v cc output r2 c = 30 pf including jig and scope gnd 90% 10% 90% 10% output v equivalent to: th venin equivalent all input pulses r th r1 rise time: 1 v/ns fall time: 1 v/ns l data retention characteristics parameter description conditions min. typ. max. unit v dr v cc for data retention 1.0 2.2 v i ccdr data retention current v cc =1.0v, ce 1 > v cc - 0.2v, ce 2 < 0.2v, v in > v cc - 0.2v or v in < 0.2v l 15 m a ll 10 t cdr [8] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns parameters 1 . 8 v unit r 1 1 3 5 0 0 w r 2 1 0 8 0 0 w r t h 6 0 0 0 w v t h 0 . 8 0 v notes: 9. full device operation requires linear v cc ramp from v dr to v cc(min.) > 100 m s or stable at v cc(min.) > 100 m s. 10. bhe . ble is the and of both bhe and ble . chip can be deselected by either disabling the chip enable signals or by disabling both bhe and ble . v cc(min.) v cc(min.) t cdr v dr > 1.0v data retention mode t r ce 1 or v cc bhe . ble ce 2 or
cy62167dv20 mobl2? document #: 38-05327 rev. *b page 5 of 10 switching characteristics (over the operating range) [11] parameter description cy62167dv20-55 cy62167dv20-70 unit min. max. min. max. read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 10 10 ns t ace ce 1 low or ce 2 high to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z [12] 5 5 ns t hzoe oe high to high z [12, 13] 20 25 ns t lzce ce 1 low or ce 2 high to low z [12] 10 10 ns t hzce ce 1 high or ce 2 low to high z [12, 13] 20 25 ns t pu ce 1 low or ce 2 high to power-up 0 0 ns t pd ce 1 high or ce 2 low to power-down 55 70 ns t dbe ble / bhe low to data valid 55 70 ns t lzbe [10] ble / bhe low to low z [12] 10 5 ns t hzbe ble / bhe high to high-z [12, 13] 20 25 ns write cycle [14] t wc write cycle time 55 70 ns t sce ce 1 low or ce 2 high to write end 40 60 ns t aw address set-up to write end 40 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 45 ns t bw ble / bhe low to write end 45 60 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high z [12, 13] 20 25 ns t lzwe we high to low z [12] 10 10 ns switching waveforms read cycle no. 1 (address transition controlled) [15, 16] notes: 11. test conditions assume signal transition time of 2 ns or less, timing reference levels of v cc(typ.)/2 , input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol . 12. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 13. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 14. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il . 15. device is continuously selected. oe , ce1 = v il , ce2 = v ih 16. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha
cy62167dv20 mobl2? document #: 38-05327 rev. *b page 6 of 10 read cycle no. 2 ( oe controlled) [16, 17] write cycle no. 1 ( we controlled) [14, 18, 19, 20] notes: 17. address valid prior to or coincident with ce 1 , bhe , ble transition low and ce 2 transition high. 18. data i/o is high-impedance if oe = v ih . 19. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in a high-impedance state. 20. during the don't care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. switching waveforms (continued) 50% 50% data valid t t t t t t high impedance t t high oe ce 1 i cc i sb impedance address ce 2 v cc supply current t bhe / ble t t data out t rc ace pd hzce hzbe hzoe lzbe doe lzoe lzce dbe pu t t t t t t t t t data in valid ce 1 address ce 2 we data i/o oe bhe / ble t don't care wc sce sa aw pwe ha bw hd sd hzoe
cy62167dv20 mobl2? document #: 38-05327 rev. *b page 7 of 10 write cycle no. 2 ( ce1 or ce2 controlled ) [14, 18, 19, 20] write cycle no. 3 ( we controlled, oe low) [19, 20] switching waveforms (continued) t t t t t t t t data in valid ce 1 address ce 2 we data i/o oe bhe / ble t t don't care wc sce ha aw sa pwe bw sd hd hzoe data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce 1 address ce 2 we data i/o don't care
cy62167dv20 mobl2? document #: 38-05327 rev. *b page 8 of 10 write cycle no. 4( bhe/ble controlled, oe low) [19] switching waveforms (continued) data i/o address t t t t t t ce 1 we data in valid t bhe / ble t ce 2 t don't care wc sce aw ha pwe sa hd sd bw truth table ce 1 ce 2 we oe bhe ble input / outputs mode power h x x x x x high z deselect/power-down standby ( i sb ) x l x x x x high z deselect/power-down standby ( i sb ) x x x x h h high z deselect/power-down standby ( i sb ) l h h l l l data out (i/o0 ? i/o15) read active ( i cc ) l h h l h l data out (i/o0 ? i/o7); high z (i/o8 ? i/o15) read active ( i cc ) l h h l l h high z (i/o0 ? i/o7); data out (i/o8 ? i/o15) read active ( i cc ) l h h h l h high z output disabled active ( i cc ) l h h h h l high z output disabled active ( i cc ) l h h h l l high z output disabled active ( i cc ) l h l x l l data in (i/o0 ? i/o15) write active ( i cc ) l h l x h l data in (i/o0 ? i/o7); high z (i/o8 ? i/o15) write active ( i cc ) l h l x l h high z (i/o0 ? i/o7); data in (i/o8 ? i/o15) write active ( i cc )
cy62167dv20 mobl2? document #: 38-05327 rev. *b page 9 of 10 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semicon ductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license under patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi ng so indemnifies cypress semiconductor against all charges. package diagrams mobl is a registered trademark, and mobl2 and more battery life are trademarks, of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. ordering information speed (ns) ordering code package name package type operating range 55 CY62167DV20L-55bvi bv48b 48-ball fine pitch bga (8.0 x 9.5 x 1.0 mm) industrial CY62167DV20Ll-55bvi bv48b 48-ball fine pitch bga (8.0 x 9.5 x 1.0 mm) 70 CY62167DV20L-70bvi bv48b 48-ball fine pitch bga (8.0 x 9.5 x 1.0 mm) industrial CY62167DV20Ll-70bvi bv48b 48-ball fine pitch bga (8.0 x 9.5 x 1.0 mm) 48-lead vfbga (8 x 9.5 x 1 mm) bv48b 51-85178-**
cy62167dv20 mobl2? document #: 38-05327 rev. *b page 10 of 10 document history page document title: cy62167dv20 mobl2? 16-mb (1024k x 16) static ram document number: 38-05327 rev. ecn no. issue date orig. of change description of change ** 118407 09/30/02 gug new data sheet a 123691 02/11/03 dpm changed advance information to preliminary added package diagram b 131496 11/25/03 xrj/ldz changed from preliminary to final added mobl2 ? to title added package name bv48b
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